A. Field of the Invention
This invention relates to electronic switching circuitry, and more particularly to a temperature compensated switching circuit and method for a junction field effect transistor (FET).
B. Description of the Prior Art
Junction FET technology has been used to successfully implement analog switches in monolithic integrated circuit forms. In such circuits a voltage is applied to the gate of the switching FET to establish an "off" condition when the FET is in a non-conducting or high impedance state, and an "on" condition when the FET presents a relatively small resistance.
FIG. 1 is a sectional diagram of a junction FET which may be employed as a switching element. The device, a bipolar p-channel FET, is shown for purposes of illustrating the temperature and operating characteristics of FETs. Other FET designs are also in use which exhibit analogous characteristics, and the invention described herein is applicable to all such devices. The device shown in FIG. 1, however, is generally capable of greater manufacturing control over certain parameters such as pinch-off voltage than are other junction FET constructions, such as n-channels.
A lightly doped p-type wafer 2 provides a substrate upon which a similarly lightly doped n-type epitaxial layer 4 is formed. Heavily doped p-type diffusions 6 and 8 are spaced along the upper portion of the epitaxial layer, with a heavily doped n-type diffusion 10 to one side of p-type diffusions 6 and 8. A p-type ion implant 12 connects the p-type diffusions and serves as the FET channel. Overlying channel 12, p-type diffusion 6, n-type diffusion 10 and at least a portion of p-type diffusion 8 is an n-type ion implant 14 which makes contact with the epitaxial layer 4. An insulating layer of silicon dioxide 16 overlies the structure described thus far, and has openings to provide access to the diffusion areas.
Source, drain and gate contacts, labeled S, D and G, are respectively made on implant area 14 over p-type diffusions 6 and 8, and n-type diffusion 10. Epitaxial layer 4 and ion implant 14 together surround channel 12 and function as the FET gate. In operation, channel 12 conducts current in response to a voltage differential across the source and drain. The application of a gate potential more positive in polarity than the source potential reduces the effective cross-sectional channel area, thereby reducing the current flow. At a certain gate voltage, denoted the pinch-off voltage, the channel becomes depleted of current carriers and the FET stops conducting current.
One of the advantages of a junction FET switch such as that just described is that, unlike a CMOS analog switch, its on-resistance remains relatively constant with analog voltage variations at low currents. However, the on-resistance of the junction FET varies considerably with temperature, typically in a directly proportional relationship of about 0.8-1.0 percent/.degree.C., and can vary by as much as 100 percent or more from -55.degree. C. to 125.degree. C. (the standard military temperature range). This strong temperature dependence limits the utility of such switches in many applications.
The temperature dependance of a junction FET results from changes in the conductivity of the channel material and in the semiconductor barrier potential as the temperature varies. The channel resistance may be expressed as: EQU R=(rL)/A (1)
where R is the channel resistance, r is the bulk resistivity, L is the channel length, and A is the channel cross-sectional area. In general, r varies positively with temperature over the military range. A varies along the length of the channel according to the voltage gradient between source and drain and the relative gate voltage, and is also a temperature-dependent parameter because of the change in junction depletion layer width with temperature.
In an attempt to compensate for the temperature effect, monolithic analog switches have been designed with low on-resistances to be able to tolerate the large resistance variations. This is accomplished by configuring the circuit driver to hold the gate-source voltage of the switching FET at zero volts when the switch is in the "on" state. However, very low on-resistances require a very large FET switching device. This makes the device less economical to produce, and the increased switch capacitance imposes speed limitation on its operation. These factors contribute to a continued widespread use of electromechanical switches.